From Python to silicon
 

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cookbook:bitonic [2006/10/04 08:16]
guenter Fixed a typo
cookbook:bitonic [2012/10/17 19:39] (current)
jandecaluwe [Verilog generation and synthesis]
Line 245: Line 245:
  
 The sorter design can be converted to Verilog as usual, with the ''toVerilog'' function. See the The sorter design can be converted to Verilog as usual, with the ''toVerilog'' function. See the
-[[cookbook:bitonic:verilog]] for the result. Note that it is a "net list of always blocks", with all structure and recursion flattend out.+[[cookbook:bitonic:verilog]] for the result. Note that it is a "net list of always blocks", with all structure and recursion flattened out.
  
 Of course, you will want to verify that the generated Verilog code is correct. This can be done by using Verilog co-simulation with the same test bench as used for the MyHDL code. You can find the details about the procedure [[cookbook:sinecomp#verilog_co-simulation|here]]. Of course, you will want to verify that the generated Verilog code is correct. This can be done by using Verilog co-simulation with the same test bench as used for the MyHDL code. You can find the details about the procedure [[cookbook:sinecomp#verilog_co-simulation|here]].
  
 To get an idea of the hardware implementation characteristics, check out the [[cookbook:bitonic:synthesis]]. To get an idea of the hardware implementation characteristics, check out the [[cookbook:bitonic:synthesis]].
cookbook/bitonic.txt ยท Last modified: 2012/10/17 19:39 by jandecaluwe
 
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