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cookbook:jc2 [2006/02/09 09:28]
jandecaluwe
cookbook:jc2 [2006/02/21 09:02] (current)
jandecaluwe
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 ====== Johnson Counter ====== ====== Johnson Counter ======
  
-===== Specification =====+===== Introduction =====
  
-On this page we will present the design of a reversable 4 bit Johnson counter. A Johnson counter has a special structure that permits glitch-free decoding. It basically consists of a circular shift register with an invertor in the loop.+On this page we will present the design of a reversable 4 bit Johnson counter. A Johnson counter has a special structure that permits glitch-free decoding.
  
 This example is originally from the Xilinx ISE design environment. If you wish, you can This example is originally from the Xilinx ISE design environment. If you wish, you can
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 to review the original design and use it as a reference. to review the original design and use it as a reference.
  
-The specification is as follows:+===== What you will learn ===== 
 + 
 +On this page you will learn about the following MyHDL features and techniques: 
 + 
 +    * modelling a counter 
 +    * writing a test bench for the counter and simulating it 
 +    * automatic conversion to Verilog 
 + 
 +===== Specification ===== 
 + 
 +A Johnson counter basically consists of a circular shift register with an invertor in the loop. 
 + 
 +The specification of the counter operation is as follows:
  
     The counter is triggered on the rising edge of the clock (clk).      The counter is triggered on the rising edge of the clock (clk). 
cookbook/jc2.txt · Last modified: 2006/02/21 09:02 by jandecaluwe
 
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