From Python to silicon
 

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cookbook:sinecomp [2006/05/04 09:02]
jandecaluwe
cookbook:sinecomp [2006/05/04 09:12] (current)
jandecaluwe
Line 487: Line 487:
 First, the convertor uses arithmetic shift (''%%>>>%%'') instead of bit-wise shift (''%%>>%%''), to have the sign bit shifted in instead of a zero. First, the convertor uses arithmetic shift (''%%>>>%%'') instead of bit-wise shift (''%%>>%%''), to have the sign bit shifted in instead of a zero.
  
-Secondly, the second (unsigned) operand is typecasted to ''$signed''. Otherwise, Verilog will interprete all operands in a mixed expression as unsigned. Having said that, the Verilog literature seems to indicate that a shift operation is an exception to this rule. But the convertor doesn't take risks and inserts the typecast as a general measure. It may be redundant in this case.+Secondly, the second (unsigned) operand is typecasted to ''$signed'', after adding a sign bit. Otherwise, Verilog will interprete all operands in a mixed expression as unsigned. Having said that, the Verilog literature seems to indicate that a shift operation is an exception to this rule. But the convertor doesn't take risks and inserts the typecast as a general measure. It may be redundant in this case.
  
 Finally, the whole expression is typecasted to ''$signed''. Actually, I would have expected that this typecast would not be necessary - after all, we are shifting a signed number. However, my current simulator (Cver) tells me that it is. It may be wrong, I don't know. Anyway, the cast is an additional safety net. Finally, the whole expression is typecasted to ''$signed''. Actually, I would have expected that this typecast would not be necessary - after all, we are shifting a signed number. However, my current simulator (Cver) tells me that it is. It may be wrong, I don't know. Anyway, the cast is an additional safety net.
cookbook/sinecomp.txt ยท Last modified: 2006/05/04 09:12 by jandecaluwe
 
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