From Python to silicon
[[MyHDL 0.8]]
 

MyHDL 0.8

Major new features:

  • modular bit vector types
  • always_seq decorator that infers the reset functionality automatically

Minor new features:

  • timescale directive for traceSignals, to set timescale in VCD file
  • toVHDL.library setting
dev/0.8.txt · Last modified: 2012/07/04 12:04 by jandecaluwe
 
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki