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MyHDL 0.8
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MyHDL 0.8
Welcome to MyHDL
The Development Zone
Introduction
Guide for developers
Source code repository
Documentation (under development)
Open tasks
MyHDL 0.8
Ideas and Draft Proposals
myhdl.org
VHDL Cosimulation with GHDL
Initial Value Support
MyHDL Enhancement Proposals
Development Archive
Terms of Use
MyHDL 0.8
Major new features:
modular bit vector types
always_seq
decorator that infers the reset functionality automatically
Minor new features:
timescale
directive for
traceSignals
, to set timescale in VCD file
toVHDL.library
setting
dev/0.8.txt · Last modified: 2012/07/04 12:04 by jandecaluwe
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