From Python to silicon


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dev:initial_values [2012/07/04 19:34]
cfelton [Some Results]
dev:initial_values [2012/07/04 19:54] (current)
cfelton [Some Results]
Line 71: Line 71:
   2. The initial block for RAM init values didn't   2. The initial block for RAM init values didn't
-     error during synthesis and generated initial +     error during synthesis.  Not clear if the  
-     values for the RAM.+     initial values would be loaded (file generated)
-  3. ROM no BRAM used for ROM tested at size +  3. TBD
-     8x2048?+
 Xilinx ISE (13.4) VHDL Xilinx ISE (13.4) VHDL
dev/initial_values.txt · Last modified: 2012/07/04 19:54 by cfelton
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