From Python to silicon
 

To do for MyHDL 0.5

To do for 0.5.1

0.5.1 has been released

  • solve bug with right shifting of negative numbers - use arithmetic shift in Verilog
  • solve inconsistency bug with Python versions in setup.py
  • toVerilog:
    • review shortcutting boolean operations, may be too restrictive
    • use if instead of case with a single test
  • document undocumented feature to hide MyHDL code from the Verilog convertor, using ”if __debug__

To do for 0.5

0.5 has been released.

  • User-defined Verilog: error handling
    • acceptable values of the driven attribute
    • error messages when exceptions occur with user-defined code
    • __toVerilog__ not supported in generator functions
  • signed arithmetic:
    • investigate fine-grained approach
  • use base classes for Enum and EnumItem, so that type-checking is possible
  • miscellaneous:
    • check typo bug with signal tracing
    • check simulation suspend mechanism
  • decorators:
    • investigate approach to remove limitations on @always decorator
    • infer specialized _Waiter class depending on sensitivity list
  • verification and error reporting:
    • argument tests on @always
    • test waiter inference for @always and @always_comb
    • argument tests on @instance
  • get feedback on style issues
    • clk.posedge instead of posedge(clk)
    • promoting general usage of decorators
  • Update documentation …
    • update what's new document
    • add note on positive numbers returned by slicing of intbv
    • make full pass over manual with new info
dev/todo/0.5.txt · Last modified: 2006/10/19 08:17 by jandecaluwe
 
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