From Python to silicon

Cosimulation using Quartus Simulator

The following code snippet is used in Cordic Calculations to verify the convertered myhdl code.

    system("quartus_map VectorCalc --generate_functional_sim_netlist")
    system("quartus_sim VectorCalc --mode=functional --vector_source=%s --simulation_results_format=VCD --check_outputs=on"%vectorsource)

The quartus simulator takes the vcd file which was created using traceSignals(). Unfortunately this only works with the top hierarchy level. Therefore the patch described in the Hierarchy Depth Feature Request ( ) must be applied and the traceSignal hierarchy dept then reduced by adding


What you finally get from quartus_sim is something like that:

Info: Simulation results from db/VectorCalc.sim.vcd (0 ps to 2.452 us) match expected results from vector source file VectorCalc.vcd
Info: Quartus II Simulator was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Nov 23 19:05:57 2007
    Info: Elapsed time: 00:00:22
projects/cosimulation_with_quartus.txt · Last modified: 2007/11/23 18:06 by thomastraber
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