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[[FT245R]]
 

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projects:ft245r [2009/03/27 06:34]
guenter Updated drawing
projects:ft245r [2011/05/03 20:07] (current)
guenter Link to datasheet updated
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 The first challenge to this interface is the bidirectional data bus. There is an enhancement proposal [[meps:mep-103|MEP 103 "Tristate and bidirectional signals"]] that describes a possible MyHDL solution to this, but it is only implemented for simulation so far. Another approach is to provide some Verilog or VHDL code that splits up the bidirectional bus into a read and a write bus. That is the approach used in this case. The [[projects:ft245r:ft245if_v]] file contains the Verilog code to provide the bus split as shown in the following figure: The first challenge to this interface is the bidirectional data bus. There is an enhancement proposal [[meps:mep-103|MEP 103 "Tristate and bidirectional signals"]] that describes a possible MyHDL solution to this, but it is only implemented for simulation so far. Another approach is to provide some Verilog or VHDL code that splits up the bidirectional bus into a read and a write bus. That is the approach used in this case. The [[projects:ft245r:ft245if_v]] file contains the Verilog code to provide the bus split as shown in the following figure:
  
-{{ :projects:ft245:bidir_bus1.png |Bidirectional bus to read and write bus conversion}}+{{ :projects:ft245:bidir_bus.png |Bidirectional bus to read and write bus conversion}}
  
 ===== Write cycle ===== ===== Write cycle =====
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   * [[http://www.ftdichip.com/Products/FT245R.htm|FTDI's  FT245R page]]   * [[http://www.ftdichip.com/Products/FT245R.htm|FTDI's  FT245R page]]
-  * [[http://www.ftdichip.com/Documents/DataSheets/DS_FT245R.pdf|FT245R datasheet]]+  * [[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT245R.pdf|FT245R datasheet]]
projects/ft245r.1238135685.txt.gz ยท Last modified: 2009/03/27 06:34 by guenter
 
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