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projects:gcicexample [2009/11/17 08:24]
cfelton
projects:gcicexample [2009/11/17 08:25] (current)
cfelton
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     toVerilog(cic, clk, rst, x, dvi, y, dvo, M, D, R)     toVerilog(cic, clk, rst, x, dvi, y, dvo, M, D, R)
 </code> </code>
- 
 ===== Results ===== ===== Results =====
 The following are the simulation results (frequency response), example of digital waveforms, and the converted Verilog and VHDL. The following are the simulation results (frequency response), example of digital waveforms, and the converted Verilog and VHDL.
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 {{ :projects:myhdl_cic_freq_response2_m1_d5_r0.png?400 }} {{ :projects:myhdl_cic_freq_response2_m1_d5_r0.png?400 }}
  
-Verilog Synthesis RTL Schematic+Verilog Synthesis RTL Schematic for an FPGA.
 {{ :projects:cic_verilog_rtl_schematic2.jpg?800 }} {{ :projects:cic_verilog_rtl_schematic2.jpg?800 }}
  
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-CIC Decimator Table: MyHDL CIC Filter compared to the Xilinx CIC Compiler+CIC Decimator Table: MyHDL CIC Filter compared to the Xilinx FPGA CIC Compiler
 ^                 ^ Rate (R) ^ Stages (M) ^ Input     ^ Output ^ Slices ^ LUTs ^ FFs ^ DSP48s ^ Fmax  ^ Target    ^ ^                 ^ Rate (R) ^ Stages (M) ^ Input     ^ Output ^ Slices ^ LUTs ^ FFs ^ DSP48s ^ Fmax  ^ Target    ^
 ^ Decimation      ^          ^            ^ Width (Q) ^ Width  ^        ^      ^     ^        ^ (MHz) ^ Device    ^     ^ Decimation      ^          ^            ^ Width (Q) ^ Width  ^        ^      ^     ^        ^ (MHz) ^ Device    ^    
projects/gcicexample.txt ยท Last modified: 2009/11/17 08:25 by cfelton
 
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