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projects:gciexample:m1d5r0verilog [2008/07/19 14:41] (current)
cfelton created
Line 1: Line 1:
 +<code verilog>
 +// File: cic.v
 +// Generated by MyHDL 0.6dev8
 +// Date: Sun Jul 13 17:46:08 2008
 +
 +`timescale 1ns/10ps
 +
 +module cic (
 +    clk,
 +    rst,
 +    x,
 +    y,
 +    dv
 +);
 +
 +input clk;
 +input rst;
 +input signed [7:0] x;
 +output signed [10:0] y;
 +reg signed [10:0] y;
 +input dv;
 +
 +reg signed [10:0] Acci_0_x;
 +reg signed [7:0] Cmbi_0_subx;
 +reg signed [7:0] Cmbi_0_dlyi_4_x;
 +reg signed [7:0] Cmbi_0_dlyi_3_x;
 +reg signed [7:0] Cmbi_0_dlyi_2_x;
 +reg signed [7:0] Cmbi_0_dlyi_1_x;
 +
 +reg [10:0] xacc [0:1-1];
 +
 +
 +always @(posedge clk) begin: CIC_CMBI_0_RTL
 +    if (rst) begin
 +        Acci_0_x <= 0;
 +    end
 +    else begin
 +        Acci_0_x <= (x - Cmbi_0_subx);
 +    end
 +end
 +
 +always @(posedge clk) begin: CIC_CMBI_0_DLYI_0_RTL
 +    Cmbi_0_dlyi_1_x <= x;
 +end
 +
 +always @(posedge clk) begin: CIC_CMBI_0_DLYI_1_RTL
 +    Cmbi_0_dlyi_2_x <= Cmbi_0_dlyi_1_x;
 +end
 +
 +always @(posedge clk) begin: CIC_CMBI_0_DLYI_2_RTL
 +    Cmbi_0_dlyi_3_x <= Cmbi_0_dlyi_2_x;
 +end
 +
 +always @(posedge clk) begin: CIC_CMBI_0_DLYI_3_RTL
 +    Cmbi_0_dlyi_4_x <= Cmbi_0_dlyi_3_x;
 +end
 +
 +always @(posedge clk) begin: CIC_CMBI_0_DLYI_4_RTL
 +    Cmbi_0_subx <= Cmbi_0_dlyi_4_x;
 +end
 +
 +always @(posedge clk) begin: CIC_ACCI_0_RTL
 +    if (rst) begin
 +        y <= 0;
 +    end
 +    else begin
 +        y <= (y + Acci_0_x);
 +    end
 +end
 +
 +endmodule
 +
 +</code>
  
projects/gciexample/m1d5r0verilog.txt ยท Last modified: 2008/07/19 14:41 by cfelton
 
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