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projects:gciexample:m1d5r0vhdl [2008/08/18 13:03] (current)
cfelton created
Line 1: Line 1:
 +<code vhdl>
 +-- File: cic.vhd
 +-- Generated by MyHDL 0.6dev8
 +-- Date: Fri Aug 15 07:53:39 2008
  
 +library IEEE;
 +use IEEE.std_logic_1164.all;
 +use IEEE.numeric_std.all;
 +use std.textio.all;
 +
 +use work.pck_myhdl_06dev8.all;
 +
 +entity cic is
 +    port (
 +        clk: in std_logic;
 +        rst: in std_logic;
 +        x: in signed (7 downto 0);
 +        dvi: in std_logic;
 +        y: out signed (11 downto 0);
 +        dvo: out std_logic
 +    );
 +end entity cic;
 +
 +architecture MyHDL of cic is
 +
 +signal xi: signed (11 downto 0);
 +signal dvoi: std_logic;
 +signal Dec_x: signed (11 downto 0);
 +signal Acci_0_dvo: std_logic;
 +signal Acci_0_x: signed (11 downto 0);
 +signal Cmbi_0_dvo: std_logic;
 +signal Cmbi_0_subx: signed (11 downto 0);
 +signal Cmbi_0_dlyi_4_x: signed (11 downto 0);
 +signal Cmbi_0_dlyi_3_x: signed (11 downto 0);
 +signal Cmbi_0_dlyi_2_x: signed (11 downto 0);
 +signal Cmbi_0_dlyi_1_x: signed (11 downto 0);
 +
 +begin
 +
 +
 +CIC_CMBI_0_RTL: process (clk) is
 +begin
 +    if rising_edge(clk) then
 +        if to_boolean(rst) then
 +            Acci_0_x <= "000000000000";
 +        else
 +            if to_boolean(dvoi) then
 +                Acci_0_x <= (xi - Cmbi_0_subx);
 +                Cmbi_0_dvo <= '1';
 +            else
 +                Cmbi_0_dvo <= '0';
 +            end if;
 +        end if;
 +    end if;
 +end process CIC_CMBI_0_RTL;
 +
 +CIC_CMBI_0_DLYI_0_RTL: process (clk) is
 +begin
 +    if rising_edge(clk) then
 +        if to_boolean(dvoi) then
 +            Cmbi_0_dlyi_1_x <= xi;
 +        end if;
 +    end if;
 +end process CIC_CMBI_0_DLYI_0_RTL;
 +
 +CIC_CMBI_0_DLYI_1_RTL: process (clk) is
 +begin
 +    if rising_edge(clk) then
 +        if to_boolean(dvoi) then
 +            Cmbi_0_dlyi_2_x <= Cmbi_0_dlyi_1_x;
 +        end if;
 +    end if;
 +end process CIC_CMBI_0_DLYI_1_RTL;
 +
 +CIC_CMBI_0_DLYI_2_RTL: process (clk) is
 +begin
 +    if rising_edge(clk) then
 +        if to_boolean(dvoi) then
 +            Cmbi_0_dlyi_3_x <= Cmbi_0_dlyi_2_x;
 +        end if;
 +    end if;
 +end process CIC_CMBI_0_DLYI_2_RTL;
 +
 +CIC_CMBI_0_DLYI_3_RTL: process (clk) is
 +begin
 +    if rising_edge(clk) then
 +        if to_boolean(dvoi) then
 +            Cmbi_0_dlyi_4_x <= Cmbi_0_dlyi_3_x;
 +        end if;
 +    end if;
 +end process CIC_CMBI_0_DLYI_3_RTL;
 +
 +CIC_CMBI_0_DLYI_4_RTL: process (clk) is
 +begin
 +    if rising_edge(clk) then
 +        if to_boolean(dvoi) then
 +            Cmbi_0_subx <= Cmbi_0_dlyi_4_x;
 +        end if;
 +    end if;
 +end process CIC_CMBI_0_DLYI_4_RTL;
 +
 +CIC_ACCI_0_RTL: process (clk) is
 +begin
 +    if rising_edge(clk) then
 +        if to_boolean(rst) then
 +            Dec_x <= "000000000000";
 +        else
 +            if to_boolean(dvoi) then
 +                Dec_x <= (Dec_x + Acci_0_x);
 +                Acci_0_dvo <= '1';
 +            else
 +                Acci_0_dvo <= '0';
 +            end if;
 +        end if;
 +    end if;
 +end process CIC_ACCI_0_RTL;
 +
 +
 +y <= Dec_x;
 +dvo <= dvoi;
 +
 +
 +xi <= resize(x, 12);
 +dvoi <= dvi;
 +
 +end architecture MyHDL;
 +
 +</code>
projects/gciexample/m1d5r0vhdl.txt ยท Last modified: 2008/08/18 13:03 by cfelton
 
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