Users & Projects

This page lists a number of MyHDL users and projects. The best thing you can do to support MyHDL is to add your project here and let people know about it! To make it easy to navigate to your projects, you can add the links to the sidebar page.

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• Continuous Sinus Waveform Generator
• UART/RS232 Receiver Transmitter
• Python Hardware Processor

I am working on processor cores suitable for SoC use. Two have been translated from Verilog into MyHDL, these are:

James Bowman's j1 a Novix style stack engine which supports multiple instructions in each 16b code word.

Bernd Paysan's b16 which is derived from the work of Chuck Moore, and has been used in real silicon.

These processors are ideal for hardware exploration and debug using simple interactive tools. Potentially, the incremental software compiler and test environment can target the hardware, or the MyHDL model.

Actel/Microsemi Igloo Nano dev kit: MyHDL source available to access and play with LEDs, switches, and UART link on this low power board.

Please email me for more info.

Dillon Engineering uses MyHDL in its verification flow. Read more about it here.

• Using MyHDL and eispice:How to connect eispice and MyHDL.
• Cordic Calculations: enhanced version of the cookbook example (Cordic-based Sine Computer).
• Sine Wave Generator using Sigma Delta DAC: using Cordic Calculations and DSX1000: Delta-Sigma DAC core
• Cosimulation using Quartus Simulator
• Get rid of the Signal: Proposal for syntax enhancement of MyHDL
• Interactive Simulation with IPython

Christopher L. Felton has used MyHDL for student projects at the University of Colorado, Colorado Springs. Using MyHDL for DSP algorithm to hardware implementations. Also uses MyHDL in a USB FPGA project (MyHDL USB FPGA page).

• DesignWest 2013 white-paper and presentation
• Configurable CIC Filter
• Recursive FFT ( source code)
• Fixed Point Package ( source code)
• IIR Filter ( source code)
• Recursive running sum filter using modbv
• USB FPGA Development Boards
• MyHDL-FPGA Tutorial
• Try MyHDL @EDAPLayground

More examples/projects under development here.

• Constellation encoder using intbv.signed()
• Complex Math
• Rounding
• FT245R interface
• MIPS32
  • MIPS32 Assembler
  • MIPS32 Single Cycle Processor, Post on mailing list with MyHDL-code
• Call Xilinx ISE from Python

Jan Decaluwe is the creator and maintainer of MyHDL, and he uses MyHDL in his consultancy practice. He also writes about HDL-based design.

• Link to SoftCore myBlaze on OpenCores

David Brochart uses MyHDL in his open-source Turbo Decoder project.

David MacQuigg uses MyHDL in a Lab Course at the university of Arizona.

Jean Demartini uses MyHDL to support a teaching course “Programmable Digital Processor Architecture” at the Engineering School of the University of Nice Sophia-Antipolis (ESINSA).

George Pantazopoulos has built an digital/analog hybrid synthesizer (codenamed the PhoenixSID 65x81) based on the Commodore 64's 6581 'SID' sound chip.

George has also released some open-source MyHDL IP cores, and has worked on an extension library to MyHDL.

George's personal page

I'm working on a project called NoCmodel: MyHDL is used for verification and code generation.

Run MyHDL simulations from your web browser. EDA Playground is specifically designed for small prototypes and examples.

MyHDL examples on EDA Playground:

• DFF
• RAM
• Sine Computer