From Python to silicon
 

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projects:mixedmodesimulation [2008/07/20 06:30]
jandecaluwe
projects:mixedmodesimulation [2008/07/20 06:31] (current)
jandecaluwe
Line 20: Line 20:
  
  
-== First Experiment ==+===== First Experiment =====
  
 In this first example we use a MyHDL clock generator to trigger a  resonant circuit with a current pulse. At the same port we read the voltage back to MyHDL (adc). In MyHDL we look if the adc voltage execeeds our limit and deliver and set the detector output voltage of the seconde PyB device to 100V. In this first example we use a MyHDL clock generator to trigger a  resonant circuit with a current pulse. At the same port we read the voltage back to MyHDL (adc). In MyHDL we look if the adc voltage execeeds our limit and deliver and set the detector output voltage of the seconde PyB device to 100V.
projects/mixedmodesimulation.txt ยท Last modified: 2008/07/20 06:31 by jandecaluwe
 
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