From Python to silicon
 

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

user:cfelton:projects:wrap [2011/04/12 11:53]
cfelton
user:cfelton:projects:wrap [2011/04/23 22:29] (current)
jandecaluwe
Line 26: Line 26:
  
 ====== Conversion ====== ====== Conversion ======
-Conversion, the conversion methods will need to identify the wrap() function and ignore it.  The underlying Verilog/VHDL binary words, signed of unsigned, behave as indented in this case.+Conversion, the conversion methods will need to identify the wrap() function and ignore it.  The underlying Verilog/VHDL binary words, signed of unsigned, behave as intended in this case.
    
 +
 ====== Example ====== ====== Example ======
 x = intbv(0, min=-8, max=7) x = intbv(0, min=-8, max=7)
user/cfelton/projects/wrap.txt ยท Last modified: 2011/04/23 22:29 by jandecaluwe
 
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki