MyHDL implementation of Gnu Radio USRP Verilog

Use at your own risk this is a project that has been started and currently in development.

This is an implementation of the Gnu Radio USRP Verilog. For the most part this is a direct port and not much attempt has been made to make it more pythonic. But rather the old structure and names have been preserved to make it more friendly to those already familiar with the USRP verilog.

Gnu Radio USRP SDR Lib

@TODO add files

users/cfelton/projects/gnu_radio.txt · Last modified: 2010/01/13 18:30 by cfelton
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