From Python to silicon

MyHDL Open Cores

Use at your own risk this is a project that has been started and currently in development.

This is a collection of basic digital components. Many of these components have been used in the USB FPGA Development Boards project.

MyHDL Cores

@TODO add code

  • SPI Controller
  • TWI Controller
  • USART Controller

users/cfelton/projects/myhdl_oc.txt · Last modified: 2010/01/13 18:30 by cfelton
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