From Python to silicon

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USB Controller Model

The following diagram shows the components of the USB controller and the USB interface. The USB controller is modeled with MyHDL. MyHDL and Python make it easy to model the behavior of the USB controller.

Interface Functions

In a testbench simple functions can be used to drive the bus transactors:

  • Write(data, ep)
  • Read(ep)
  • IsEmpty(ep)
  • IsData(ep)
  • WriteAddress(addr, data)
  • ReadAddress(addr)

Testbench Example Using the FX2 Model

        yield fx2Model.WriteAddress(0x0101, 1)       # Write Wishbone memory mapped device 
        yield fx2Model.WriteAddress(0x0103, 0xAA)    # Write Wishbone memory mapped device
        yield fx2Model.ReadAddress(0x0103, rbuf)
        yld =
        while yld is not None:
            yield yld
            yld =
        print "    GPIO read %x " % (rbuf[0])
        TracePrint('Test Reads and Writes 1')
        for dat in test_data1:
            fx2Model.Write(dat, fx2Model.EP4)        
        TracePrint('Wait for write fifo empty')
        while not fx2Model.IsEmpty(fx2Model.EP4):
            yield delay(2*fx2Model.IFCLK_TICK)
        TracePrint('Wait for data in read fifo')
        while not fx2Model.IsData(fx2Model.EP8, 5):
            yield delay(2*fx2Model.IFCLK_TICK)
        for dat in test_data1:
            rdata = fx2Model.Read(fx2Model.EP8)
            assert rdata == dat, \
             "Testbench FAILED return data %x expected %x" % (rdata, dat)
        yield delay(20*fx2Model.IFCLK_TICK)

Some of the USB controller functions will be a generator and will return a valid MyHDL yield type. Majority of the functions do complicated tasks that require the simulation engine to run and to wait for events.

users/cfelton/projects/usb_model.1252068755.txt.gz · Last modified: 2009/09/04 12:52 by cfelton
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