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users:cfelton:projects:usb_model [2009/09/04 12:52] cfelton |
users:cfelton:projects:usb_model [2009/09/04 12:55] (current) cfelton |
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yield fx2Model.WriteAddress(0x0103, 0xAA) # Write Wishbone memory mapped device | yield fx2Model.WriteAddress(0x0103, 0xAA) # Write Wishbone memory mapped device | ||
yield fx2Model.ReadAddress(0x0103, rbuf) | yield fx2Model.ReadAddress(0x0103, rbuf) | ||
- | yld = gen.next() | + | |
- | while yld is not None: | + | # Write data to the FX2 Model |
- | yield yld | + | |
- | yld = gen.next() | + | |
- | + | ||
- | print " GPIO read %x " % (rbuf[0]) | + | |
- | + | ||
- | + | ||
- | #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | + | |
- | TracePrint('Test Reads and Writes 1') | + | |
for dat in test_data1: | for dat in test_data1: | ||
fx2Model.Write(dat, fx2Model.EP4) | fx2Model.Write(dat, fx2Model.EP4) | ||
- | TracePrint('Wait for write fifo empty') | + | # Wait for the data to transfer |
- | while not fx2Model.IsEmpty(fx2Model.EP4): | + | yield fx2Model.IsEmpty(fx2Model.EP4) |
- | yield delay(2*fx2Model.IFCLK_TICK) | + | |
+ | # Wait for data in FIFO | ||
+ | yield fx2Model.IsData(fx2Model.EP8, 5) | ||
- | TracePrint('Wait for data in read fifo') | + | |
- | while not fx2Model.IsData(fx2Model.EP8, 5): | + | # Read Data out of the FX2 |
- | yield delay(2*fx2Model.IFCLK_TICK) | + | |
for dat in test_data1: | for dat in test_data1: | ||
rdata = fx2Model.Read(fx2Model.EP8) | rdata = fx2Model.Read(fx2Model.EP8) |