From Python to silicon
 

USB FPGA Development Boards

This is a project in development. The project pages are incomplete and source is under development (incomplete).

Introduction

This project includes the development of an interface to the Cypress FX2 high speed USB controller. The FX2 controller is popular in many FPGA development boards. These boards include, DSPtronics, USBP, OpalKelly, Digilent, GnuRadio USRP, ZTEX, Zest, and others. The interface includes a streaming pipe and a pipe that commands a wishbone controller. These provide high speed (30MBytes / sec) data and control communication to the FPGA. The USBP firmware is used for the FX2 controller. This firmware provides two CDC/ACM (virtual comm port) one for each of the pipes.

This project will encompass a USB interface framework for FPGA development boards. The design and implementation is covered in the following sections.

USB Controller Model

FPGA USB Interface Design

Latest Developments

Revision Comment
0.9pre Added the Xilinx xise files for 11.x ISE versions
0.8pre General enhancements/fixes to USB interface. Added external audio CODEC interfaces

Setup and Install

This section describes how to install the various MyHDL (Python) packages to simulate and synthesize this design. Installing the drivers and host software is beyond the scope of this page. For more information on the driver and host installation see USBP

Downloads
Moving to repo, check back soon or post to newsgroup for questions.

To run this project first download the above archive and unzip.

This will extract to the following directory structure.

  - usbp -+ 
          - fpga_projects
          - open_cores
          - top_levels/
                  - usbp_myhdl/usbp_myhdl.py
          - usbp_cores    

Then run » python setup.py install. This will install the open_cores and usbp_cores Python packages.

This project has been broken up to a couple different Python packages and directories.

  • USBP cores : This package includes the modules for the USB interface. Includes the Wishbone controller and streaming interface.
  • Open cores : This package is the MyHDL implementation of modules freely available. All these modules are Wishbone compatible.
  • Top levels : This includes the top-level HDL and top-level testbenches.
  • FPGA project files : This includes example FPGA vendor tool projects.

To run the top-level testbench

>> cd usbp/top_levels/usbp_myhdl/
>> python test_usbp.py

The testbench will generate a VCD file which can be viewed with GTKWave.

GTKWave VCD View

To generate Verilog and VHDL

>> python usbp_myhdl.py

Synthesizing the Design

To synthesize and PAR the design simply open the Xilinx ISE project(s) in the fpga_projects/ise directory. Currently the usbp/fpga_projects/ise/my_usbp/my_usbp_111/ is an 11.1 ISE project for the USBP UFO-400 board.

Get the Code

The MyHDL code (cores) have been slowly moving to https://github.com/cfelton/minnesota. And I intend to use the fpgalink software, http://www.makestuff.eu/wordpress/software/fpgalink/.

(OLD) Revision History

The following are older revisions. See above for the latest code and links to revisions.

Revision Comment
0.8pre General enhancements/fixes to USB interface. Added external audio CODEC interfaces
0.5pre Created a single distribution archive
0.3pre Fixed an issue with the distribution, not all packages were included.
0.2pre Embedded a simple ramp generator into the design. This can be used as a simple verification method during run-time.
users/cfelton/projects/usbp.txt · Last modified: 2013/08/01 16:40 by cfelton
 
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki