From Python to silicon
 

George Pantazopoulos

I really love MyHDL!

Tools I currently use

  • Electronic Design Automation
    • MyHDL
    • Xilinx WebPACK ISE 8.1.03i
    • Cadsoft Eagle Layout Editor (circuit board design)
    • Digilent Sparatan3 Development board
    • Tektronix 2215 60MHz oscilloscope
  • Python Programming
    • Python 2.4.3 (on cygwin)
    • PyGtk
    • Eclipse IDE
      • PyDev and PyDev Extensions (these Eclipse plugins rock. I just paid for a PyDev Extensions license)
  • Graphic design and Photography
    • The Gimp
    • Inkscape
    • POV-Ray & MegaPOV XRS (3D raytracing)
      • Check out Eagle3D. It lets you export Eagle board layouts into POV-Ray and render a 3-D version of your (populated) board design!
    • Canon Powerhshot SD450 digital camera (5 Megapixel, ultracompact)

Bio

Graduated from UMass Lowell Winter 2004 with a degree in Computer Science. Now living in the Boston area in Massachusetts (USA)

Music

Music is very important in my life. I enjoy combining my love of engineering with love of music. I play the guitar, keyboards, and sing, as well as write music. My favorite band is and always will be Judas Priest, and while metal is my favorite style, I also love punk, blues, electronica, 80's Freestyle, rock'n'roll, chiptunes and videogame music. Other bands I like include Nightwish, Stevie Ray Vaughan, Depeche Mode, STP, Green Day, Franz Ferdinand and much more. Also, check out SLAY Radio (C64 remixes!) when you get the chance 8-)

See also

www.gammaburst.net, My main project website (Robotics, Graphics, Music and more)

PhoenixSID 65X81

Open-source IP cores

MyHDL Booster

Background

As I work on taking PhoenixSID to the next level, I've been inventing techniques to streamline the creation of a complex design and make it much more fun.

These homegrown techniques are synergistic, and I've decided to collect them together under the title “MyHDL Booster”, which is inspired by the excellent Boost C++ libraries.

Description

MyHDL Booster is a set of Python tools and classes that simplify the design and verification of complex hardware in a way users of Verilog and VHDL can only dream of.

MyHDL Booster is intended to work as an add-on to MyHDL.

Goals
  • Streamline the design and verification of systems-on-a-chip.
    • Eliminate redundancy and automate as much as possible.
    • Do away with long, cumbersome argument lists and signal name clashes in large systems
    • Be able to construct WISHBONE systems the MyHDL way
  • Work as an add-on to MyHDL
    • Require no modifications to MyHDL itself (unless there is a compelling reason)
    • Establish “existing practice” and provide reference implementations, similar to the Boost C++ Libraries
  • Reduce or eliminate dependence on vendor-specific, proprietary tools.
  • Drive the evolution of MyHDL Booster by working on real, implementation-oriented designs
  • Get feedback from MyHDL users and developers to further improvement.
Functionality in development
  • Port grouping
    • Streamlines the interconnection of modules with many ports
    • Anticipates MyHDL support for bidirectional ports
    • Making port grouping work with toVerilog and co-simulation
  • Signal grouping
  • Using classes in hardware modelling
  • Synergistically ties together port grouping and Ascii Port Spec
  • Can provide more friendly error messages than MyHDL alone
  • Ascii Timing Spec
    • ASCII-art timing diagrams that serve a dual purpose.
      • Easily readable documentation
      • The very same diagrams can be parsed and used to drive inputs and verify outputs during regression tests.
        • Eliminates redundancy and comment drift
  • Ascii Port Spec
    • Plain-text port specification that is embedded in the docstring of a Hardware Module
    • Easily readable documentation of the ports and port groups that belong to a Hardware Module.
    • That very same documentation block can be parsed and used to automatically generate ports and port groups at instantiation time.
      • Eliminates redundancy and comment drift
  • Multi-stage unit tests
    • Support reusable stages
    • Combine traditional stages with ASCII Port Spec-driven stages
    • Made possible by combining generators
    • May benefit from small change to MyHDL so MyHDL can work with Python itertools objects, which are not of type GeneratorType
  • Regression tests without needing py.test
Demonstration code

WISHBONE & Opencores for MyHDL

  • Wrapping Verilog cores from opencores.org for use in MyHDL
  • Creating WISHBONE Bus components
    • Creating a parts library of reliable, plug-n-play components much like Lego™ blocks

MyHDL Logo Work In Progress

Snakey Draft 1

users/george_pantazopoulos.txt · Last modified: 2006/11/17 06:05 by themaxx
 
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